An electrically reloadable nonvolatile memory has more advantageous features as a memory device of an information apparatus in terms of the low power consumption, the resistance against the vibrational shock, the high speed operation and the like as compared with other devices such as a magnetic memory device and an optical disc device. On the other hand, however, since the manufacturing process thereof is complicated and in addition thereto, the operations which are in principle irreversible against semiconductor are repeatedly carried out, there arises a problem that occurrence of faulty portions and degradation in use thereof are remarkable. As a result, the manufacturing yield thereof is poor, the cost required therefor is expensive and reliability in operation thereof becomes a problem.
In order to solve the above-mentioned problems, the technique has been developed such that the faulty portions of the memory are previously registrated so as not to be used, and the number of times of use of the data blocks is recorded and then if this number of times is increased, then the region of interest is replaced with another region to suppress the increase in the number of times of use thereof, thereby increasing the life of the semiconductor memory device. This technique is disclosed in JP-A-6-124596 for example.
According to this disclosed technique, there is provided a memory for storing therein an address conversion table showing the comparison between the logical addresses and the physical addresses, i.e., the correspondence between the logical address specified by a host and the corresponding physical address on the memory. As a result, the physical address of the faulty region is registered in the address conversion table so as to show that it is faulty so that the logical address specified by the host is not assigned thereto, thereby preventing the faulty portion from being used.
In addition, the number of times of erasing is administrated. That is, if the number of times of erasing has reached a fixed value, then the data of the region of interest is replaced with the data of another region and at the same time, the address values on the address conversion table are reloaded to register again the data relating to the correspondence between the logical addresses and the physical addresses so that the proper correspondence therebetween can be obtained. All of the logical address values in use are registered in the above-mentioned address conversion table. Then, the high speed volatile memory such as a DRAM or an SRAM is used as the storage medium for the address conversion table.
The reason of employing the high speed volatile memory is that the address conversion can be carried out at a high speed; when the replacement of the address of interest with another address occurs, the registration can be partially reloaded at a high speed; the mass storage of the data can be realized by utilizing the relatively inexpensive memory; and so forth.
In the above-mentioned prior art, since the registration of the address conversion is carried out with respect to all of the logical addresses, when the memory device becomes of mass storage, the scale of the address conversion table becomes large and hence the mass storage memory for registration is required. In addition, since the memory device is of a volatile type, if the power source is disconnected, then all of the data stored therein will be erased. As a result, when turning on the power source again, all of the registered values need to be written thereto from another nonvolatile memory and hence the time period required for the activation of the memory device is increased. This is a problem.
In addition, since the external memory for registration becomes of mass storage, there arises a problem that the number of components is increased, which disturbs the miniaturization and the promotion of lowering the cost of the memory device.
In addition, if the nonvolatile memory is employed as the above-mentioned memory for registration, then there arises a problem that since the access time of the nonvolatile memory is generally long, the access time of the memory device itself becomes necessarily long.
In addition, if the back-up power source is provided for the volatile memory for registration, then the number of components is further increased, which disturbs the miniaturization and the promotion of lowering the cost of the memory device. This is a problem.
In the light of the foregoing, it is therefore an object of the present invention to provide a mass storage semiconductor memory device, in which the miniaturization thereof and the promotion of lowering the cost thereof can be made, and also the activation time and the access time are reduced, by solving the above-mentioned problems associated with the prior art.
It is a concrete object of the present invention to provide, by either reducing the capacity of the external memory for registration or removing the external memory for registration, a mass storage semiconductor memory device in which the activation time and the access time are both short.
It is a concrete object of the present invention to provide, for use in a mass storage semiconductor memory device in which either the capacity of the external memory for registration is reduced or the external memory for registration is removed, an access method by which both of the activation time and the access time can be made short.
It is another object of the present invention to provide, for use in a mass storage semiconductor memory device in which either the capacity of the external memory for registration is reduced or the external memory for registration is removed, a controller which is capable of realizing the short activation time and access time.